RISC-V instructions

TermMeaning
immImmediate value
pcProgram counter
rdDestination register
rsSource register
sext(n)Sign extend n
x[n]Register number n
M[n]Memory at address n
<sLess than (signed)
<uLess than (unsigned)
^Bitwise Exclusive OR
|Bitwise OR
&Bitwise AND

RV32I, RV64I

add rd, rs1, rs2

Add. Adds rs1 and rs2 and puts the result in rd. Owerflow is ignored.

x[rd] = x[rs1] + x[rs2]
31 2524 2019 1514 1211 76 0
0000000rs2rs1000rd0110011
755357

RV32I, RV64I

addi rd, rs1, imm

Add immediate. Adds rs1 and imm and puts the result in rd. Arithmetic overflow is ignored.

x[rd] = x[rs1] + sext(imm)
31 2019 1514 1211 76 0
imm[11:0]rs1000rd0010011
125357

RV64I

addiw rd, rs1, imm

Add word immediate. Adds rs1 and imm and puts the result in rd. Arithmetic overflow is ignored.

x[rd] = sext((x[rs1] + sext(imm))[31:0])
31 2019 1514 1211 76 0
imm[11:0]rs1000rd0011011
125357

RV64I

addw rd, rs1, rs2

Add word. Adds rs1 and rs2 and puts the result in rd. Owerflow is ignored.

x[rd] = sext((x[rs1] + x[rs2])[31:0])
31 2524 2019 1514 1211 76 0
0000000rs2rs1000rd0111011
755357

amoadd.d


amoadd.w


amoand.d


amoand.w


amomax.d


amomaxu.d


amomaxu.w


amomax.w


amomin.d


amominu.d


amominu.w


amomin.w


amoor.d


amoor.w


amoswap.d


amoswap.w


amoxor.d


amoxor.w


RV32I, RV64I

and rd, rs1, rs2

AND. Calculates bitwise AND on rs1 and rs2 and puts the result in rd.

x[rd] = x[rs1] & x[rs2]
31 2524 2019 1514 1211 76 0
0000000rs2rs1111rd0110011
755357

RV32I, RV64I

andi rd, rs1, imm

AND immediate. Calculates bitwise AND on rs1 and imm and puts the result in rd.

x[rd] = x[rs1] & sext(imm)
31 2019 1514 1211 76 0
imm[11:0]rs1111rd0010011
125357

RV32I, RV64I

auipc rd, imm

Add upper immediate to pc. Can be used to build addresses relative to program counter. Adds imm (upper 20 bits, with lower 12 bits = 0) and pc and puts the result in rd.

x[rd] = pc + sext(imm[31:12] << 12)
31 1211 76 0
imm[31:12]rd0010111
2057

Related: lui


RV32I, RV64I

beq rs1, rs2, imm

Branch if =. Adds imm (multiple of 2) to pc if rs1 and rs2 are equal.

if (rs1 == rs2) pc += sext(imm)
31 2524 2019 1514 1211 76 0
imm[12|10:5]rs2rs1000imm[4:1|11]1100011
755357

beqz rs, imm

Branch if = zero. Pseudoinstruction.

beq rs, x0, imm

RV32I, RV64I

bge rs1, rs2, imm

Branch if ≥. Adds imm (multiple of 2) to pc if rs1 is greater than (signed) or equal to rs2.

if (rs1 ≥s rs2) pc += sext(imm)
31 2524 2019 1514 1211 76 0
imm[12|10:5]rs2rs1101imm[4:1|11]1100011
755357

RV32I, RV64I

bgeu rs1, rs2, imm

Branch if ≥, unsigned. Adds imm (multiple of 2) to pc if rs1 is greater than (unsigned) or equal to rs2.

if (rs1 ≥u rs2) pc += sext(imm)
31 2524 2019 1514 1211 76 0
imm[12|10:5]rs2rs1111imm[4:1|11]1100011
755357

bgez rs, imm

Branch if ≥ zero. Pseudoinstruction.

bge rs, x0, imm

bgt rs, rt, imm

Branch if >. Pseudoinstruction.

blt rt, rs, imm

bgtu rs, rt, imm

Branch if >, unsigned. Pseudoinstruction.

bltu rt, rs, imm

bgtz rs, imm

Branch if > zero. Pseudoinstruction.

blt x0, rs, imm

ble rs, rt, imm

Branch if ≤. Pseudoinstruction.

bge rt, rs, imm

bleu rs, rt, imm

Branch if ≤, unsigned. Pseudoinstruction.

bgeu rt, rs, imm

blez rs, imm

Branch if ≤ zero. Pseudoinstruction.

bge x0, rs, imm

RV32I, RV64I

blt rs1, rs2, imm

Branch if <. Adds imm (multiple of 2) to pc if rs1 is less than (signed) rs2.

if (rs1 <s rs2) pc += sext(imm)
31 2524 2019 1514 1211 76 0
imm[12|10:5]rs2rs1100imm[4:1|11]1100011
755357

RV32I, RV64I

bltu rs1, rs2, imm

Branch if <, unsigned. Adds imm (multiple of 2) to pc if rs1 is less than (unsigned) rs2.

if (rs1 <u rs2) pc += sext(imm)
31 2524 2019 1514 1211 76 0
imm[12|10:5]rs2rs1110imm[4:1|11]1100011
755357

bltz rs, imm

Branch if < zero. Pseudoinstruction.

blt rs, x0, imm

RV32I, RV64I

bne rs1, rs2, imm

Branch if ≠. Adds imm (multiple of 2) to pc if rs1 and rs2 are not equal.

if (rs1 ≠ rs2) pc += sext(imm)
31 2524 2019 1514 1211 76 0
imm[12|10:5]rs2rs1001imm[4:1|11]1100011
755357

bnez rs, imm

Branch if ≠ zero. Pseudoinstruction.

bne rs, x0, imm

call imm

Call far-away subroutine. Pseudoinstruction.

auipc x6, imm[31:12]
jalr x1, x6, imm[11:0]

Related: tail


RV32I, RV64I

csrrc rd csr rs1

Control and status register read and clear. Atomically writes the old value of csr to rd and clears the csr bits that are set in rs1. Unwritable bits in csr are unaffected.

If rs1 is x0 then csr is not written to and no side effects from writing to it will occur (this is not the same when rs1 is another register that holds value 0).

t = CSRs[csr]
CSRs[csr] = t & ∼x[rs1]
x[rd] = t
31 2019 1514 1211 76 0
csrrs1011rd1110011
125357

RV32I, RV64I

csrrci rd csr imm[4:0]

Control and status register read and clear immediate. Atomically writes the old value of csr to rd and clears the csr bits that are set in imm. Unwritable bits in csr are unaffected.

If imm is 0 then csr is not written to and no side effects from writing to it will occur.

t = CSRs[csr]
CSRs[csr] = t & ∼imm
x[rd] = t
31 2019 1514 1211 76 0
csrimm111rd1110011
125357

RV32I, RV64I

csrrs rd, csr, rs1

Control and status register read and set. Atomically writes the old value of csr to rd and sets the csr bits that are set in rs1. Unwritable bits in csr are unaffected.

If rs1 is x0 then csr is not written to and no side effects from writing to it will occur (this is not the same when rs1 is another register that holds value 0).

t = CSRs[csr]
CSRs[csr] = t | x[rs1]
x[rd] = t
31 2019 1514 1211 76 0
csrrs1010rd1110011
125357

RV32I, RV64I

csrrsi rd, csr, imm[4:0]

Control and status register read and set immediate. Atomically writes the old value of csr to rd and sets the csr bits that are set in imm. Unwritable bits in csr are unaffected.

If imm is 0 then csr is not written to and no side effects from writing to it will occur.

t = CSRs[csr]
CSRs[csr] = t | imm
x[rd] = t
31 2019 1514 1211 76 0
csrimm110rd1110011
125357

RV32I, RV64I

csrrw rd, csr, rs1

Control and status register read and write. Atomically writes the old value of csr to rd and rs1 to csr.

If rd is x0 then csr is not read and no side effects from reading it will occur.

t = CSRs[csr]
CSRs[csr] = x[rs1]
x[rd] = t
31 2019 1514 1211 76 0
csrrs1001rd1110011
125357

RV32I, RV64I

csrrwi rd, csr, imm[4:0]

Control and status register read and write immediate. Atomically writes the old value of csr to rd and imm to csr.

If rd is x0 then csr is not read and no side effects from reading it will occur.

t = CSRs[csr]
CSRs[csr] = imm
x[rd] = t
31 2019 1514 1211 76 0
csrimm101rd1110011
125357

div


divu


divuw


divw


RV32I, RV64I

ebreak

Environment breakpoint. Used by debuggers to cause control to be transferred back to the debugger.

RaiseException(Breakpoint)
31 2019 1514 1211 76 0
00000000000100000000000001110011
125357

RV32I, RV64I

ecall

Environment call. Makes a request to the supporting execution environment (usually the operating system).

RaiseException(EnvironmentCall)
31 2019 1514 1211 76 0
00000000000000000000000001110011
125357

fabs.d rd, rs

Double-precision absolute value. Pseudoinstruction.

fsgnjx.d rd, rs, rs

fabs.s rd, rs

Single-precision absolute value. Pseudoinstruction.

fsgnjx.s rd, rs, rs

fadd.d


fadd.s


fclass.d


fclass.s


fcvt.d.l


fcvt.d.lu


fcvt.d.s


fcvt.d.w


fcvt.d.wu


fcvt.l.d


fcvt.l.s


fcvt.lu.d


fcvt.lu.s


fcvt.s.d


fcvt.s.l


fcvt.s.lu


fcvt.s.w


fcvt.s.wu


fcvt.w.d


fcvt.w.s


fcvt.wu.d


fcvt.wu.s


fdiv.d


fdiv.s


RV32I, RV64I

fence pred, succ

Fence memory and I/O. Ensures that no operation following the fence (that is specified in succ) can be observed before any operation preceding the fence (that is specified in pred), by any other RISC-V hart or external device.

pred and succ are 4 bit values specifying the types of operations: [Input | Output | Read | Write]. Any combination may be specified.

Fence(pred, succ)
31 2019 1514 1211 76 0
0000 | pred | succ00000000000000001111
125357

fence

Fence on all memory and I/O. Pseudoinstruction.

fence iorw, iorw

RV32I, RV64I

fence.i

Fence instruction stream. Ensures that a subsequent instruction fetch on a RISC-V hart will see any previous data stores already visible to the same RISC-V hart. It does not ensure that other RISC-V harts will see the stores.

Fence(Store, Fetch)
31 2019 1514 1211 76 0
imm[11:0]00000001000000001111
125357

feq.d


feq.s


fld


fld rd, imm, rt

Floating-point load doubleword. Pseudoinstruction.

auipc rt, imm[31:12]
fld rd, imm[11:0](rt)

fle.d


fle.s


flt.d


flt.s


flw


flw rd, imm, rt

Floating-point load word. Pseudoinstruction.

auipc rt, imm[31:12]
flw rd, imm[11:0](rt)

fmadd.d


fmadd.s


fmax.d


fmax.s


fmin.d


fmin.s


fmsub.d


fmsub.s


fmul.d


fmul.s


fmv.d rd, rs

Copy double-precision register. Pseudoinstruction.

fsgnj.d rd, rs, rs

fmv.d.x


fmv.s rd, rs

Copy single-precision register. Pseudoinstruction.

fsgnj.s rd, rs, rs

fmv.w.x


fmv.x.d


fmv.x.w


fneg.d rd, rs

Double-precision negate. Pseudoinstruction.

fsgnjn.d rd, rs, rs

fneg.s rd, rs

Single-precision negate. Pseudoinstruction.

fsgnjn.s rd, rs, rs

fnmadd.d


fnmadd.s


fnmsub.d


fnmsub.s


fsd


fsd rd, imm, rt

Floating-point store doubleword. Pseudoinstruction.

auipc rt, imm[31:12]
fsd rd, imm[11:0](rt)

fsgnj.d


fsgnjn.d


fsgnjn.s


fsgnj.s


fsgnjx.d


fsgnjx.s


fsqrt.d


fsqrt.s


fsub.d


fsub.s


fsw


fsw rd, imm, rt

Floating-point store word. Pseudoinstruction.

auipc rt, imm[31:12]
fsw rd, imm[11:0](rt)

j imm

Jump. Pseudoinstruction.

jal x0, imm

RV32I, RV64I

jal rd, imm

Jump and link. Adds imm (multiple of 2 bytes) to pc. Puts the address of the instruction following the jump (pc + 4 before adding) in rd.

x[rd] = pc + 4
pc += sext(imm)
31 1211 76 0
imm[20|10:1|11|19:12]rd1101111
2057

Related: jalr


jal imm

Jump and link. Pseudoinstruction.

jal x1, imm

RV32I, RV64I

jalr rd, imm(rs1)

Jump and link register. Adds imm and rs1, clears the least-significant bit and puts the result in pc. Puts the address of the instruction following the jump (pc + 4 before changing pc) in rd.

t = pc + 4
pc = (x[rs1] + sext(imm)) & ∼1
x[rd] = t
31 2019 1514 1211 76 0
imm[11:0]rs1000rd1100111
125357

Related: jal call tail


jalr rs

Jump and link register. Pseudoinstruction.

jalr x1, rs, 0

jr rs

Jump register. Pseudoinstruction.

jalr x0, rs, 0

la rd, imm

Load address. Pseudoinstruction.

auipc rd, imm[31:12]
addi rd, rd, imm[11:0]

RV32I, RV64I

lb rd, imm(rs1)

Load byte. Copies byte from memory at address imm+rs1 into register rd.

x[rd] = sext(M[x[rs1] + sext(imm)][7:0])
31 2019 1514 1211 76 0
imm[11:0]rs1000rd0000011
125357

Related: lbu, sb


lb rd, imm

Load byte. Pseudoinstruction.

auipc rd, imm[31:12]
lb rd, imm[11:0](rd)

RV32I, RV64I

lbu rd, imm(rs1)

Load byte, unsigned. Copies byte from memory at address imm+rs1 into register rd.

x[rd] = M[x[rs1] + sext(imm)][7:0]
31 2019 1514 1211 76 0
imm[11:0]rs1100rd0000011
125357

Related: lb, sb


RV64I

ld rd, imm(rs1)

Load doubleword. Copies doubleword from memory at address imm+rs1 into register rd.

x[rd] = sext(M[x[rs1] + sext(imm)][63:0])
31 2019 1514 1211 76 0
imm[11:0]rs1011rd0000011
125357

Related: sd


ld rd, imm

Load doubleword. Pseudoinstruction.

auipc rd, imm[31:12]
ld rd, imm[11:0](rd)

RV32I, RV64I

lh rd, imm(rs1)

Load halfword. Copies halfword from memory at address imm+rs1 into register rd.

x[rd] = sext(M[x[rs1] + sext(imm)][15:0])
31 2019 1514 1211 76 0
imm[11:0]rs1001rd0000011
125357

Related: lhu, sh


lh rd, imm

Load halfword. Pseudoinstruction.

auipc rd, imm[31:12]
lh rd, imm[11:0](rd)

RV32I, RV64I

lhu rd, imm(rs1)

Load halfword, unsigned. Copies halfword from memory at address imm+rs1 into register rd.

x[rd] = M[x[rs1] + sext(imm)][15:0]
31 2019 1514 1211 76 0
imm[11:0]rs1101rd0000011
125357

Related: lh, sh


li rd, imm

Load immediate. Pseudoinstruction.


lr.d


lr.w


RV32I, RV64I

lui rd, imm

Load upper immediate. Can be used to build 32-bit constants. Puts upper 20 bits of imm in rd and fills lower 12 bits with zeros.

x[rd] = sext(imm[31:12] << 12)
31 1211 76 0
imm[31:12]rd0110111
2057

Related: li, auipc


RV32I, RV64I

lw rd, imm(rs1)

Load word. Copies word from memory at address imm+rs1 into register rd.

x[rd] = sext(M[x[rs1] + sext(imm)][31:0])
31 2019 1514 1211 76 0
imm[11:0]rs1010rd0000011
125357

Related: sw


lw rd, imm

Load word. Pseudoinstruction.

auipc rd, imm[31:12]
lw rd, imm[11:0](rd)

RV64I

lwu rd, imm(rs1)

Load word, unsigned. Copies word from memory at address imm+rs1 into register rd.

x[rd] = M[x[rs1] + sext(imm)][31:0]
31 2019 1514 1211 76 0
imm[11:0]rs1110rd0000011
125357

Related: lw


mul


mulh


mulhsu


mulhu


mulw


mv rd, rs

Copy register. Pseudoinstruction.

addi rd, rs, 0

neg rd, rs

Two's complement. Pseudoinstruction.

sub rd, x0, rs

negw rd, rs

Two's complement word. Pseudoinstruction.

subw rd, x0, rs

nop

No operation. Pseudoinstruction.

addi x0, x0, 0

not rd, rs

One's complement. Pseudoinstruction.

xori rd, rs, -1

RV32I, RV64I

or rd, rs1, rs2

OR. Calculates bitwise OR on rs1 and rs2 and puts the result in rd.

x[rd] = x[rs1] | x[rs2]
31 2524 2019 1514 1211 76 0
0000000rs2rs1110rd0110011
755357

RV32I, RV64I

ori rd, rs1, imm

OR immediate. Calculates bitwise OR on rs1 and imm and puts the result in rd.

x[rd] = x[rs1] | sext(imm)
31 2019 1514 1211 76 0
imm[11:0]rs1110rd0010011
125357

rem


remu


remuw


remw


ret

Return from subroutine. Pseudoinstruction.

jalr x0, x1, 0

RV32I, RV64I

sb rs2, imm(rs1)

Store byte. Copies register rs2 as byte into memory at address imm+rs1.

M[x[rs1] + sext(imm)] = x[rs2][7:0]
31 2524 2019 1514 1211 76 0
imm[11:5]rs2rs1000imm[4:0]0100011
755357

Related: lb


sb rd, imm, rt

Store byte. Pseudoinstruction.

auipc rt, imm[31:12]
sb rd, imm[11:0](rt)

sc.d


sc.w


RV64I

sd rs2, imm(rs1)

Store doubleword. Copies register rs2 as doubleword into memory at address imm+rs1.

M[x[rs1] + sext(imm)] = x[rs2][63:0]
31 2524 2019 1514 1211 76 0
imm[11:5]rs2rs1011imm[4:0]0100011
755357

Related: ld


sd rd, imm, rt

Store doubleword. Pseudoinstruction.

auipc rt, imm[31:12]
sd rd, imm[11:0](rt)

sext.w rd, rs

Sign extend word. Pseudoinstruction.

addiw rd, rs, 0

seqz rd, rs

Set if = zero. Pseudoinstruction.

sltiu rd, rs, 1

sgtz rd, rs

Set if > zero. Pseudoinstruction.

slt rd, x0, rs

RV32I, RV64I

sh rs2, imm(rs1)

Store halfword. Copies register rs2 as halfword into memory at address imm+rs1.

M[x[rs1] + sext(imm)] = x[rs2][15:0]
31 2524 2019 1514 1211 76 0
imm[11:5]rs2rs1001imm[4:0]0100011
755357

Related: lh


sh rd, imm, rt

Store halfword. Pseudoinstruction.

auipc rt, imm[31:12]
sh rd, imm[11:0](rt)

RV32I, RV64I

sll rd, rs1, rs2

Shift left logical. Shifts rs1 left rs2 bits and puts the result in rd. The lower bits are filled with zeros. Only the lower 5 bits (RV32I) or 6 bits (RV64I) in rs2 are used.

x[rd] = x[rs1] << x[rs2]
31 2524 2019 1514 1211 76 0
0000000rs2rs1001rd0110011
755357

Related: srl


RV32I

slli rd, rs1, imm

Shift left logical immediate. Shifts rs1 left imm bits. The lower bits are filled with zeros.

x[rd] = x[rs1] << imm
31 2019 1514 1211 76 0
0000000 | imm[4:0]rs1001rd0010011
125357

Related: srli


RV64I

slli rd, rs1, imm

Shift left logical immediate. Shifts rs1 left imm bits. The lower bits are filled with zeros.

x[rd] = x[rs1] << imm
31 2019 1514 1211 76 0
000000 | imm[5:0]rs1001rd0010011
125357

Related: srli


RV64I

slliw rd, rs1, imm

Shift left logical word immediate. Shifts rs1 left imm bits. The lower bits are filled with zeros. imm[5] must be 0.

x[rd] = sext((x[rs1] << imm)[31:0])
31 2019 1514 1211 76 0
000000 | imm[5:0]rs1001rd0011011
125357

Related: srliw


RV64I

sllw rd, rs1, rs2

Shift left logical word. Shifts rs1 left rs2 bits and puts the result in rd. The lower bits are filled with zeros. Only the lower 5 bits of rs2 are used.

x[rd] = sext((x[rs1] << x[rs2][4:0])[31:0])
31 2524 2019 1514 1211 76 0
0000000rs2rs1001rd0111011
755357

Related: srlw


RV32I, RV64I

slt rd, rs1, rs2

Set if <. Puts 1 in rd if rs1 is less than (signed) rs2, else 0 is written to rd.

x[rd] = x[rs1] <s x[rs2]
31 2524 2019 1514 1211 76 0
0000000rs2rs1010rd0110011
755357

RV32I, RV64I

slti rd, rs1, imm

Set if < immediate. Puts 1 in rd if rs1 is less than (signed) imm, else 0 is written to rd.

x[rd] = x[rs1] <s sext(imm)
31 2019 1514 1211 76 0
imm[11:0]rs1010rd0010011
125357

RV32I, RV64I

sltiu rd, rs1, imm

Set if < immediate, unsigned. Puts 1 in rd if rs1 is less than (unsigned) imm, else 0 is written to rd.

x[rd] = x[rs1] <u sext(imm)
31 2019 1514 1211 76 0
imm[11:0]rs1011rd0010011
125357

RV32I, RV64I

sltu rd, rs1, rs2

Set if <, unsigned. Puts 1 in rd if rs1 is less than (unsigned) rs2, else 0 is written to rd.

x[rd] = x[rs1] <u x[rs2]
31 2524 2019 1514 1211 76 0
0000000rs2rs1011rd0110011
755357

sltz rd, rs

Set if < zero. Pseudoinstruction.

slt rd, rs, x0

snez rd, rs

Set if ≠ zero. Pseudoinstruction.

sltu rd, x0, rs

RV32I, RV64I

sra rd, rs1, rs2

Shift right arithmetic. Shifts rs1 right rs2 bits and puts the result in rd. The upper bits are filled with the original sign bit. Only the lower 5 bits (RV32I) or 6 bits (RV64I) in rs2 are used.

x[rd] = x[rs1] >>s x[rs2]
31 2524 2019 1514 1211 76 0
0100000rs2rs1101rd0110011
755357

Related: srl


RV32I

srai rd, rs1, imm

Shift right arithmetic immediate. Shifts rs1 right imm bits. The upper bits are filled with the original sign bit.

x[rd] = x[rs1] >>s imm
31 2019 1514 1211 76 0
0100000 | imm[4:0]rs1101rd0010011
125357

Related: srli


RV64I

srai rd, rs1, imm

Shift right arithmetic immediate. Shifts rs1 right imm bits. The upper bits are filled with the original sign bit.

x[rd] = x[rs1] >>s imm
31 2019 1514 1211 76 0
010000 | imm[5:0]rs1101rd0010011
125357

Related: srli


RV64I

sraiw rd, rs1, imm

Shift right arithmetic word immediate. Shifts rs1 right imm bits. The upper bits are filled with the original sign bit.

x[rd] = sext(x[rs1][31:0] >>s imm)
31 2019 1514 1211 76 0
010000 | imm[5:0]rs1101rd0011011
125357

Related: srliw


RV64I

sraw rd, rs1, rs2

Shift right arithmetic word. Shifts rs1 right rs2 bits and puts the result in rd. The upper bits are filled with the original sign bit. Only the lower 5 bits in rs2 are used.

x[rd] = sext(x[rs1][31:0] >>s x[rs2][4:0])
31 2524 2019 1514 1211 76 0
0100000rs2rs1101rd0111011
755357

Related: srlw


RV32I, RV64I

srl rd, rs1, rs2

Shift right logical. Shifts rs1 right rs2 bits and puts the result in rd. The upper bits are filled with zeros. Only the lower 5 bits (RV32I) or 6 bits (RV64I) in rs2 are used.

x[rd] = x[rs1] >> x[rs2]
31 2524 2019 1514 1211 76 0
0000000rs2rs1101rd0110011
755357

Related: sll sra


RV32I

srli rd, rs1, imm

Shift right logical immediate. Shifts rs1 right imm bits. The upper bits are filled with zeros.

x[rd] = x[rs1] >>u imm
31 2019 1514 1211 76 0
0000000 | imm[4:0]rs1101rd0010011
125357

Related: slli, srai


RV64I

srli rd, rs1, imm

Shift right logical immediate. Shifts rs1 right imm bits. The upper bits are filled with zeros.

x[rd] = x[rs1] >>u imm
31 2019 1514 1211 76 0
000000 | imm[5:0]rs1101rd0010011
125357

Related: slli, srai


RV64I

srliw rd, rs1, imm

Shift right logical word immediate. Shifts rs1 right imm bits. The upper bits are filled with zeros. imm[5] must be 0.

x[rd] = sext(x[rs1][31:0] >>u imm)
31 2019 1514 1211 76 0
000000 | imm[5:0]rs1101rd0011011
125357

Related: slliw, sraiw


RV64I

srlw rd, rs1, rs2

Shift right logical word. Shifts rs1 right rs2 bits and puts the result in rd. The upper bits are filled with zeros. Only the lower 5 bits in rs2 are used.

x[rd] = sext(x[rs1][31:0] >>u x[rs2][4:0])
31 2524 2019 1514 1211 76 0
0000000rs2rs1101rd0111011
755357

Related: sllw sraw


RV32I, RV64I

sub rd, rs1, rs2

Subtract. Subtracts rs2 from rs1 and puts the result in rd. Owerflow is ignored.

x[rd] = x[rs1] - x[rs2]
31 2524 2019 1514 1211 76 0
0100000rs2rs1000rd0110011
755357

RV64I

subw rd, rs1, rs2

Subtract word. Subtracts rs2 from rs1 and puts the result in rd. Owerflow is ignored.

x[rd] = sext((x[rs1] - x[rs2])[31:0])
31 2524 2019 1514 1211 76 0
0100000rs2rs1000rd0111011
755357

RV32I, RV64I

sw rs2, imm(rs1)

Store word. Copies register rs2 as word into memory at address imm+rs1.

M[x[rs1] + sext(imm)] = x[rs2][31:0]
31 2524 2019 1514 1211 76 0
imm[11:5]rs2rs1010imm[4:0]0100011
755357

Related: lw


sw rd, imm, rt

Store word. Pseudoinstruction.

auipc rt, imm[31:12]
sw rd, imm[11:0](rt)

tail imm

Tail call far-away subroutine. Pseudoinstruction.

auipc x6, imm[31:12]
jalr x0, x6, imm[11:0]

Related: call


RV32I, RV64I

xor rd, rs1, rs2

Exclusive OR. Calculates bitwise XOR on rs1 and rs2 and puts the result in rd.

x[rd] = x[rs1] ^ x[rs2]
31 2524 2019 1514 1211 76 0
0000000rs2rs1100rd0110011
755357

RV32I, RV64I

xori rd, rs1, imm

Exclusive OR immediate. Calculates bitwise XOR on rs1 and imm and puts the result in rd.

x[rd] = x[rs1] ^ sext(imm)
31 2019 1514 1211 76 0
imm[11:0]rs1100rd0010011
125357